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power management 1 www.semtech.com sc2441a 1.8v to 20v input 2-phase synchronous step-down controllers with step-up converter description revision: february 04, 2009 the sc2441a is a programmable frequency dual independent or dual/multiple phase single output peak current-mode step-down switching regulator controller. it is capable of operating from 1.8v to 20v input. a 0.6a step-up converter in the sc2441a generates an auxiliary gate drive supply when vin is below 4.5v. this makes the sc2441a well suited for applications where a low-voltage input (<3.3v) is to be stepped down for lower voltage logic, yet the input is too low to drive power mosfets efficiently. the sc2441a employs a phase-locked synchronizing circuit that allows the step-up converter to operate at twice the switching frequency of the step-down controllers for miniaturization. the clock output signal enables two or more sc2441as to be daisy chained with programmable phase shift. tying the fb2 pin to vin makes the second step-down channel a slave of the first. operating in this mode, the sc2441a regulates a single output with shared current in each channel. each step-down controller has its own soft- start and overload shutdown timer for hiccup overload protection. in the single-output mode, the channel 1 timer controls the soft-start and overload hiccup of both controllers. features applications low voltage distributed dc-dc converters telecommunication power supplies servers and base stations 2-phase synchronous step-down controllers 2-phase synchronous continuous conduction mode out of phase operation for low input current ripple operates up to 1mhz per channel excellent current sharing between phases duty cycle up to 90% 0.5v feedback voltages for low-voltage outputs starts into pre-biased outputs adaptive shoot-through protection lossless inductor dcr current sensing 23mv current-limit threshold individual soft-start, overload hiccup and enable step-up regulator 0.27v v cesat switch at 0.6a fixed frequency current-mode control common features wide input voltage range: 1.8v to 20v synchronizing frequency equal to that of the step- down converters 28-lead tssop-edp lead-free package, fully weee and rohs compliant typical application circuit figure 1 r21 c3 vin rcs+2 c21 r26 vcc r23 r2 vcc c8 d4 r11 u1 27 24 19 18 11 26 6 4 28 12 3 5 17 13 14 8 15 16 2 7 25 23 22 20 21 10 9 1 sw3 pgnd1 gdh2 bst2 fb1 pgnd2 sync/shdn cs1+ ckout comp1 ss1/en1 cs1- ss2/en2 comp2 fb2 comp3 cs2- cs2+ pllf fb3 bst1 gdh1 gdl1 gdl2 vc c rosc gnd in r15 r16 r19 vout1 r1 c22 l2 r8 vcc signal ground c24 r9 r24 c26 r13 power ground r4 l3 c25 q3 c6 q2 r10 r18 l1 c5 c20 c7 r20 r25 r12 d1 c19 c23 d2 c13 d3 q4 r7 r3 c11 d5 vout2 vin c4 c2 c1 r27 rcs+1 r6 r5 c9 q1 c12 sc2441a
2 ? 2006 semtech corp. www.semtech.com power management sc2441a absolute maximum rating electrical characteristics exceeding the specifications below may result in permanent damage to the device, or device malfunction. operation outside of th e parameters specified in the electrical characteristics section is not implied. r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u t u o k c o l e g a t l o v r e d n u v c c d l o h s e r h t t r a t sv h t c c v c c g n i s a e r c n i5 4 . 45 5 . 4v v c c s i s e r e t s y h o l v uv l t c c v c c g n i s a e r c e d0 5 1v m v c c t n e r r u c t u p n ii c c v c c v , v 8 = s / s v 2 = v c c v , v 4 = l t c c v , s / s v 2 = v c c v , v 8 = s / s ) 2 ( v 0 = 0 1 5 0 . 0 8 5 1 0 . 1 1 1 a m s r e i f i l p m a r o r r e 2 d n a 1 l e n n a h c e g a t l o v k c a b d e e fv , 1 b f v 2 b f v n i v 5 , v 3 =v < c c v 0 1 <4 9 4 . 00 0 5 . 06 0 5 . 0v v n i v 5 , v 3 =v < c c , v 0 1 < c 5 8 o t c 0 4 - 5 9 4 . 00 0 5 . 05 0 5 . 0v t n e r r u c s a i b t u p n i n i p k c a b d e e f i 1 b f 0 6 -0 0 2 -a n i 2 b f 0 8 2 -0 0 5 -a n e c n a t c u d n o c s n a r t r e i f i l p m ag , 1 m g 2 m 5 1 3 ? 1 ? n i a g e g a t l o v p o o l n e p oa 1 o a , 2 o 5 7b d h t d i w d n a b n i a g y t i n u r e i f i l p m a) 1 e t o n (5z h m t n e r r u c k n i s t u p t u o r e i f i l p m av 2 , 1 b f v , v 1 = 2 , 1 p m o c v 5 . 2 =6 14 29 2 a t n e r r u c e c r u o s t u p t u o r e i f i l p m av 2 , 1 b f v , v 0 = 2 , 1 p m o c v 5 . 2 =93 16 1 a unless specified: v in = 2v, v cc = v bst1 = v bst2 =8v, sync/shdn =2v, rosc = 51.1k ? , -40c < t a = t j < 105c r e t e m a r a pl o b m y ss g n i t a r m u m i x a ms t i n u e g a t l o v t u p n iv n i 0 2 o t 3 . 0 -v r e l l o r t n o c n w o d - p e t s r o f e g a t l o v y l p p u sv c c 0 2 o t 3 . 0 -v s e g a t l o v y l p p u s r e v i r d e d i s - h g i hv 1 t s b v , 2 t s b 8 2 o t 3 . 0 -v e g a t l o v 2 b f , 1 b fv 1 b f v , 2 b f 0 2 o t 3 . 0 -v s e g a t l o v 2 p m o c , 1 p m o cv 1 p m o c v , 2 p m o c 5 . 4 o t 3 . 0 -v ) - ( 2 s c d n a ) + ( 2 s c , ) - ( 1 s c , ) + ( 1 s c s e g a t l o v v , ) + ( 1 s c v ) - ( 1 s c v , ) + ( 2 s c ,v ) - ( 2 s c v o t 3 . 0 - c c v e g a t l o v n d h s / c n y sv s / s v o t 3 . 0 - n i 1 +v e g a t l o v c s o rv c s o r 2 o t 3 . 0 -v s e g a t l o v 2 n e / 2 s s d n a 1 n e / 1 s sv 1 s s v , 2 s s 4 o t 3 . 0 -v e g a t l o v 3 b fv 3 b f 4v e g a t l o v 3 w sv 3 w s 0 3 o t 3 . 0 -v e r u t a r e p m e t n o i t c n u j m u m i x a mt j 0 5 1c e s a c o t n o i t c n u j e c n a t s i s e r l a m r e h t c j 2w / c t n e i b m a o t n o i t c n u j e c n a t s i s e r l a m r e h t a j 7 3w / c e g n a r e r u t a r e p m e t e g a r o t st g t s 0 5 1 o t 0 6 -c c e s 0 1 ) g n i r e d l o s ( e r u t a r e p m e t d a e lt d a e l 0 0 3c ) l e d o m y d o b n a m u h ( s g n i t a r d s ed s e0 0 0 2v
3 ? 2006 semtech corp. www.semtech.com power management sc2441a electrical characteristics (cont.) unless specified: v in = 2v, v cc = v bst1 = v bst2 =8v, sync/shdn =2v, rosc = 51.1k ? , -40c < t a = t j < 105c r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u n o i t a r e p o m w p r o f d l o h s e r h t p m o c v ) + ( 1 s c =v ) - ( 1 s c 0 = v ) + ( 2 s c =v ) - ( 2 s c 0 = 7 6 . 15 8 . 15 0 . 2v t u p t u o e l g n i s e s a h p - 2 r o f e g a t l o v 2 b f n o i t a r e p o f o e d o m 5 5 . 1v p o o l d e k c o l - e s a h p d n a r o t a l l i c s o y c n e u q e r f g n i n n u r e e r ff o c c t j v ; c 5 2 = f l l p v 1 >0 5 40 0 50 5 5z h k y c n e u q e r f g n i k c o l m u m i n i mv f l l p n e p o0 4 2z h k g n i k c o l m u m i n i m / y c n e u q e r f g n i n n u r e e r f y c n e u q e r f t j c 5 2 =7 . 10 . 2 t n e r r u c t u p t u o p m u p e g r a h ci f l l p v f l l p v 1 =0 15 10 2 a e l c y c y t u d m u m i x a m d , 1 x a m d 2 x a m 8 80 9% e l c y c y t u d m u m i n i md , 1 n i m d 2 n i m 0% e g a t l o v h g i h t u p n i n d h s / c n y sv h s / s 5 . 1v e g a t l o v w o l t u p n i n d h s / c n y sv l s / s 5 . 0v t n e r r u c t u p n i n d h s / c n y si s / s v s / s v 2 . 0 = v s / s v 2 =0 4 1 0 6 a y a l e d n w o d t u h s ) 1 e t o n (5 8 s e g a t l o v h g i h t u p t u o k c o l ct u o k c h i t u o k c 0 8 - = a6 . 18 . 1v e g a t l o v w o l t u p t u o k c o l ct u o k c l i t u o k c 0 0 2 = a4 . 0v s r o t a r a p m o c t i m i l - t n e r r u c d n a m w p , s r e i f i l p m a e s n e s - t n e r r u c e g n a r e d o m n o m m o c t u p n i 0v c c 1 -v d l o h s e r h t t i m i l t n e r r u cv , 1 m i l i v 2 m i l i v c c v 8 = v ) - ( 1 s c =v ) - ( 2 s c v 0 = 8 13 28 2v m d l o h s e r h t t i m i l t n e r r u cv , 1 m i l i v 2 m i l i v c c v 8 = v ) - ( 1 s c =v ) - ( 2 s c v 5 = 8 13 28 2v m t n e r r u c s a i b t u p n i e s n e s - t n e r r u c e v i t i s o pi , ) + ( 1 s c i ) + ( 2 s c v ) + ( 1 s c =v ) - ( 1 s c 0 = v ) - ( 2 s c =v ) - ( 2 s c 0 = 4 . 0 -8 . 0 - a t n e r r u c s a i b t u p n i e s n e s - t n e r r u c e v i t a g e ni , ) - ( 1 s c i ) - ( 2 s c v ) + ( 1 s c =v ) - ( 1 s c 0 = v ) + ( 2 s c =v ) - ( 2 s c 0 = 0 4 -5 7 - a e m i t - n o m w p m u m i n i m t a 5 2 = ) 1 e t o n ( , c 0 8 1s n s r e v i r d e t a g t n e r r u c e c r u o s k a e p e v i r d e t a g e d i s - h g i h ) 1 e t o n (2a t n e r r u c k n i s k a e p e v i r d e t a g e d i s - h g i h ) 1 e t o n (2a t n e r r u c e c r u o s k a e p e v i r d e t a g e d i s - w o l ) 1 e t o n (2a
4 ? 2006 semtech corp. www.semtech.com power management sc2441a electrical characteristics (cont.) r e t e m a r a pl o b m y ss n o i t i d n o cn i mp y tx a ms t i n u t n e r r u c k n i s k a e p e v i r d e t a g e d i s - w o l ) 1 e t o n (2a e m i t e s i r e v i r d e t a gc l f p 0 0 3 3 =0 3s n e m i t l l a f e v i r d e t a gc l f p 0 0 3 3 =0 3s n e l b a n e d n a f f o t u h s d a o l r e v o , t r a t s - t f o s d a o l r e v o e l b a n e o t e g a t l o v t r a t s - t f o s p u c c i h v , 1 n e s s v 2 n e s s v 1 s s d n av 2 s s g n i s a e r c n i3 . 3v d l o h s e r h t b f p u c c i h d a o l r e v o v , 1 l o b f v 2 l o b f v 2 , 1 s s v 5 . 3 = b f 1 d n ab f 2 g n i s a e r c e d 5 3 . 08 3 . 01 4 . 0v t n e r r u c e g r a h c s i d t r a t s - t f o s i , ) s i d ( 1 s s i ) s i d ( 2 s s v 1 b f =v 2 b f =v 3 . 0 v 1 s s =v 2 s s =v 3 69 2 1 a r e t f a t r a t s e r o t e g a t l o v t r a t s - t f o s n w o d t u h s d a o l r e v o v , 1 t s r s s v 2 t s r s s v 1 s s d n av 2 s s g n i s a e r c e d5 . 0v e g a t l o v n e / s s e l b a s i d l e n n a h c 6 . 0v n o i t a r e p o m w p r o f d l o h s e r h t n e / s s v ) + ( 1 s c v = ) - ( 1 s c 0 = v ) + ( 2 s c v = ) - ( 2 s c 0 = 3 2 . 18 2 . 13 3 . 1v r e t r e v n o c t s o o b v n i d l o h s e r h t t r a t sv h t n i v n i g n i s a e r c n i3 7 . 16 7 . 1v v n i s i s e r e t s y hv l t n i 0 0 1v m t n e r r u c s a i b n i p k c a b d e e fi 3 b f 0 40 5 2a n e g a t l o v k c a b d e e fv 3 b f v < v 8 . 1 n i v 5 . 6 1 <5 2 2 . 10 5 2 . 15 7 2 . 1v e c n a t c u d n o c s n a r t r e i f i l p m a k c a b d e e fg 3 m 0 7 ? 1 - n i a g p o o l - n e p o r e i f i l p m a k c a b d e e fa 3 o 0 5b d y c n e u q e r f g n i h c t i w s r e t r e v n o c t s o o b f 3 c s o 1z h m e l c y c y t u d h c t i w s m u m i x a md 3 x a m 5 82 9 % e g a t l o v n o i t a r u t a s h c t i w s r e t r e v n o c t s o o bv t a s e c i w s a 6 . 0 =7 2 . 0v t n e r r u c e g a k a e l h c t i w s t s o o bi e g a k a e l v w s v 2 1 =5 a t i m i l t n e r r u c h c t i w s t s o o bi t i m i l 6 . 08 . 0a n w o d t u h s l a m r e h t 5 5 1c s i s e r e t s y h n w o d t u h s l a m r e h t 0 1c notes: (1) guaranteed by design not tested in production. (2) input current is dominated by the equivalent gate drive current to external mosfets in active switching condition. unless specified: v in = 2v, v cc = v bst1 = v bst2 =8v, sync/shdn =2v, rosc = 51.1k ? , -40c < t a = t j < 105c
5 ? 2006 semtech corp. www.semtech.com power management sc2441a pin configurations ordering information e c i v e de g a k c a p e r u t a r e p m e t t ( e g n a r a ) t r t e t a 1 4 4 2 c s ) 2 , 1 ( p d e - 8 2 - p o s s tc 5 8 o t 0 4 - b v e a 1 4 4 2 c sd r a o b n o i t a u l a v e notes: (1) only available in tape and reel packaging. a reel contains 2500 devices for the tssop-28-edp package. (2) lead free product. this product is fully weee and rohs compliant. 1 2 3 4 5 6 7 8 ckout in 27 28 15 16 sw3 pllf pgnd2 ss1/en1 bst1 cs1+ pgnd1 cs1- gdh1 sync/shdn gdl1 fb3 vcc comp3 9 10 22 gdl2 gnd gdh2 rosc 21 18 17 19 20 11 12 24 bst2 fb1 ss2/en2 comp1 23 25 26 13 14 cs2+ comp2 cs2- fb2 tssop-28 edp top view
6 ? 2006 semtech corp. www.semtech.com power management sc2441a pin descriptions n i pe m a n n i pn o i t c n u f n i p 1n i e t a r e n e g o t d e s u t o n s i r e t r e v n o c t s o o b f i c c v o t e i t . r e t r e v n o c t s o o b e h t r o f e g a t l o v y l p p u s . y l p p u s y r a i l i x u a 2f l l p. p o o l k c o l e s a h p e h t r o f n i p n o i t a s n e p m o c 31 n e / 1 s s r e t r e v n o c n w o d - p e t s t s r i f e h t t e s n i p s i h t o t d e i t r o t i c a p a c l a n r e t x e n a d n a r o t s i s e r l a n r e t x e n a 1 l e n n a h c f f o s t u h s v 6 . 0 w o l e b n i p s i h t g n i l l u p . e m i t e l c y c p u c c i h d a o l r e v o s t i d n a e m i t t r a t s - t f o s . s r e v i r d e t a g 4+ 1 s c . r o t a r a p m o c / r e i f i l p m a e s n e s - t n e r r u c 1 l e n n a h c e h t o t t u p n i g n i t r e v n i - n o n e h t 5- 1 s c e h t o t d e i t y l l a m r o n . r o t a r a p m o c / r e i f i l p m a e s n e s - t n e r r u c 1 l e n n a h c e h t o t t u p n i g n i t r e v n i e h t . r e t r e v n o c e h t f o t u p t u o 6n d h s / c n y s e l b a n e o t v 5 . 1 e v o b a e g a t l o v a o t r o ) 1 n i p ( n i o t n i p s i h t e i t . t u p n i n w o d t u h s d n a n o i t a z i n o r h c n y s t s o o b e h t d n a s r e l l o r t n o c n w o d - p e t s h t o b f f o s t u h s v 5 . 0 w o l e b n i p s i h t g n i l l u p . a 1 4 4 2 c s e h t r e t r e v n o c t s o o b e h t . a 1 4 4 2 c s e h t s e z i n o r h c n y s k c o l c l a n r e t x e n a h t i w n i p s i h t g n i v i r d . r o t a l u g e r e h t t a e t a r e p o s r e l l o r t n o c n w o d - p e t s e h t s a e r e h w y c n e u q e r f k c o l c l a n r e t x e e h t f o e c i w t t a s n u r . y c n e u q e r f k c o l c 73 b f 3 t u o r o f r e d i v i d e v i t s i s e r l a n r e t x e n a o t d e i t s i 3 b f . r e i f i l p m a r o r r e t s o o b o t t u p n i g n i t r e v n i e h t . g n i t t e s e g a t l o v 83 p m o c v 4 . 0 w o l e b n i p s i h t g n i l l u p . n o i t a s n e p m o c p o o l r o f d e s u . t u p t u o r e i f i l p m a r o r r e r e t r e v n o c t s o o b . r e t r e v n o c p u - p e t s e h t s e l b a s i d 9d n g. d n u o r g g o l a n a 0 1c s o r . y c n e u q e r f g n i n n u r - e e r f r o t a l l i c s o e h t s t e s d n g o t n i p s i h t m o r f d e t c e n n o c r o t s i s e r l a n r e t x e n a 1 11 b f n e e w t e b r e d i v i d e v i t s i s e r l a n r e t x e n a o t e i t . r e i f i l p m a r o r r e 1 l e n n a h c e h t o t t u p n i g n i t r e v n i e h t . g n i s n e s e g a t l o v t u p t u o r o f d n u o r g e h t d n a 1 t u o 2 11 p m o c . n o i t a s n e p m o c p o o l r o f d e s u . t u p t u o r e i f i l p m a r o r r e 1 l e n n a h c 3 12 p m o c . n o i t a s n e p m o c p o o l r o f d e s u . t u p t u o r e i f i l p m a r o r r e 2 l e n n a h c 4 12 b f n e e w t e b r e d i v i d e v i t s i s e r l a n r e t x e n a o t e i t . r e i f i l p m a r o r r e 2 l e n n a h c e h t o t t u p n i g n i t r e v n i e h t t u p t u o e l g n i s e s a h p - o w t r o f c c v r o n i o t e i t . g n i s n e s e g a t l o v t u p t u o r o f d n u o r g e h t d n a 2 t u o . n o i t a r e p o 5 1- 2 s c e h t o t d e i t y l l a m r o n . r o t a r a p m o c / r e i f i l p m a e s n e s - t n e r r u c 2 l e n n a h c e h t o t t u p n i g n i t r e v n i e h t . r e t r e v n o c e h t f o t u p t u o 6 1+ 2 s c . r o t a r a p m o c / r e i f i l p m a e s n e s - t n e r r u c 1 l e n n a h c e h t o t t u p n i g n i t r e v n i - n o n e h t 7 12 n e / 2 s s r e t r e v n o c n w o d - p e t s d n o c e s e h t t e s n i p s i h t o t d e i t r o t i c a p a c l a n r e t x e n a d n a r o t s i s e r l a n r e t x e n a 2 l e n n a h c f f o s t u h s v 6 . 0 w o l e b n i p s i h t g n i l l u p . e m i t e l c y c p u c c i h d a o l r e v o s t i d n a e m i t t r a t s - t f o s . n o i t a r e p o t u p t u o e l g n i s e s a h p - o w t r o f n e p o e v a e l . s r e v i r d e t a g 8 12 t s b n a d n a r o t i c a p a c p a r t s t o o b a o t t c e n n o c . e v i r d e t a g r e p p u 2 l e n n a h c r o f y l p p u s d e p p a r t s t o o b . e d o i d l a n r e t x e 9 12 h d g o t d n u o r g m o r f s g n i w s e g a t l o v e v i r d e t a g . t e f s o m r e p p u 2 l e n n a h c r o f t u p t u o e v i r d e t a g . 2 t s b v
7 ? 2006 semtech corp. www.semtech.com power management sc2441a pin descriptions (cont.) 0 22 l d g m o r f s g n i w s e g a t l o v e v i r d e t a g . t e f s o m s u o n o r h c n y s 2 l e n n a h c r o f t u p t u o e v i r d e t a g . c c v o t d n u o r g 1 2c c v e h t . s r e v i r d e t a g t e f s o m s u o n o r h c n y s e h t d n a s r e l l o r t n o c n w o d - p e t s h t o b r o f e g a t l o v y l p p u s s t e f s o m r e w o p e h t e c n a h n e y l l u f o t h g u o n e h g i h t o n s i n i v f i c c v s e t a r e n e g r e t r e v n o c t s o o b e i t . s r e l l o r t n o c n w o d - p e t s e h t r o f e g a t l o v y l p p u s y r a i l i x u a n a s e d i v o r p r e t r e v n o c t s o o b e h t d n a . d e d e e n t o n s i r e t r e v n o c t s o o b e h t f i n i v o t c c v 2 21 l d g m o r f s g n i w s e g a t l o v e v i r d e t a g . t e f s o m s u o n o r h c n y s 1 l e n n a h c r o f t u p t u o e v i r d e t a g . c c v o t d n u o r g 3 21 h d g o t d n u o r g m o r f s g n i w s e g a t l o v e v i r d e t a g . t e f s o m r e p p u 1 l e n n a h c r o f t u p t u o e v i r d e t a g . 1 t s b v 4 21 d n g p . s r e v i r d e t a g e h t f o n r u t e r d n u o r g r e w o p 5 21 t s b n a d n a r o t i c a p a c p a r t s t o o b a o t t c e n n o c . e v i r d e t a g r e p p u 1 l e n n a h c r o f y l p p u s d e p p a r t s t o o b . e d o i d l a n r e t x e 6 22 d n g p . r e t t i m e h c t i w s t s o o b 7 23 w s . e d o i d g n i l e e h w e e r f d n a r o t c u d n i t s o o b a o t t c e n n o c . r o t c e l l o c h c t i w s t s o o b 8 2t u o k c. ) b ( 5 e r u g i f n i m a r g a i d g n i m i t e e s . t u p t u o k c o l c d a p d e s o p x e . n o i t c u d n o c l a m r e h t e c n a h n e o t e n a l p d n u o r g l a n g i s e h t o t d e r e d l o s y l r e p o r p e b t s u m
8 ? 2006 semtech corp. www.semtech.com power management sc2441a block diagram figure 2 functional diagram of the step-down controllers in oscillator and phase detector slope1 + ilim1 clk2 r q s ol1 soft-start and overload hiccup control 1 uvlo 4.3v/4.5v adaptive shoot-through protection pwm1 ros c cs1+ cs1- clk1 - + + reference + - isen1 + - dsbl 1 vcc bst1 gdh1 gdl 1 pgnd1 25mv 23 25 24 ss1/en1 3 21 22 5 1 fb1 11 10 6 4 fault gnd 9 comp 1 12 vin uvlo 0.5v 0.35v frequency divider clk 1.25v 1.6/1.7v slope co mp shdn slope2 shdn sync/shdn gdh2 gdl 2 19 18 pllf 2 20 bst2 vcc slope2 i + ilim2 r q s ol2 soft-start and overload hiccup control 2 pwm2 fb2 cs2- - + + + - isen2 + - 25mv dsbl 2 comp 2 15 14 cs2+ 16 13 sel clk2 1.25v - + analo g switch ss2/en2 17 sel a y b adaptive shoot-through protection ea1 0.5v - + + 1.25v 2r r ckout 28 tg1on 1.25v 2r r tg2on ea2 0.5v - + + - + 1.25v - + 1.25v ch 1 ch 2 a1 mux a2 a3
9 ? 2006 semtech corp. www.semtech.com power management sc2441a block diagram figure 4 details of soft-start and overload hiccup control circuit ol (overload) 0.5v/3.3v s q r ds bl fb ss/ en + 0.35v - + 0.8v - s q r uv = ?1? if vcc < 4.5v t urn of f gate driv es r ss vcc shdn uv shdn = ? 1? i f sync/ s hdn < 0. 5v tgon fault soft-start and over load hiccup control figure 2 c ss q1 c1 c2 c3 l1 l2 hi ccup disa bl e 10 a figure 3. step-up converter functional diagram fb3 sw3 comp3 ea 3 slope comp + r q s pwm3 clk - + - + + 1.25v + - isen3 ilim3 + - i-limit 26 27 7 8 r sense pgnd2
10 2006 semtech corp. www.semtech.com power management sc2441a block diagram figure 5. phase-locked loop (a) and its timing diagram in locked condition (r 2 not used) (b). (b) (a) 1.5v - clk ckout 28 rosc 10 6 sync/shdn ext clock buffer phase / frequency detector qu qd pllf c1 r1 c2 pllf 2 1k internal clamp r2 external pll compensation optional resistor for setting phase shift current- controlled oscillator rosc toggle flip-flop qt qt sets free - runnng frequency clk1 clk2 s1 s2 + + 0.4v v/i xclk xclk clk1 qt clk2 clk gdh1 gdh2 ckout qt pllf
11 2006 semtech corp. www.semtech.com power management sc2441a figure 6a. sc2441a start-up timing diagram figure 6b. sc2441a overload hiccup operation timing diagram 1.25v 1.85v 3.3v enable hiccup 4.5v vcc v soft-start v comp v out pwm 1.25v 1.85v 3.3v v comp enable hiccup v o 0.8v 0.5v v soft-start-cap 70% x v o setpoint disable hiccup restart v o pwm
12 2006 semtech corp. www.semtech.com power management sc2441a typical characteristics feedback pin input bias current vs temperature 0 50 100 150 200 250 300 350 400 -50 -25 0 25 50 75 100 125 temperature (c) feedback pin i nput bias current (na) v comp2 = 3v channel 2 v comp1 = 3v channel 1 amplifier transconductance vs temperature 200 220 240 260 280 300 320 340 360 380 400 -50 -25 0 25 50 75 100 125 temperature (c) amplifier transconductance ( ) amplifier open loop gain vs temperature 70 71 72 73 74 75 76 77 78 79 80 -50 -25 0 25 50 75 100 125 temperature (c) amplifier open loop gain (db) step-down channel feedback vs temperature 0.45 0.47 0.49 0.51 0.53 0.55 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) v in = 3v v cc = 8v percenatge frequency deviation from nominal vs temperature -5 -4 -3 -2 -1 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature (c) deviation (% ) r osc = 40.2k r osc = 51.1k r osc = 66.5k step-down channel switching frequency vs temperature 350 400 450 500 550 600 650 -50 -25 0 25 50 75 100 125 temperature (c) frequency (khz ) r osc = 40.2k r osc = 51.1k r osc = 66.5k
13 ? 2006 semtech corp. www.semtech.com power management sc2441a typical characteristics clock output high voltage vs temperature 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 -50 -25 0 25 50 75 100 125 temperature (c) clock output high voltage (v) i clk_out = - 80 a clock output low voltage vs temperature 0.03 0.04 0.05 0.06 0.07 0.08 -50-25 0 25 50 75100125 temperature (c) clock output low voltage (v) i clk_out = 200 a charge pump current i pllf vs temperature 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 -50-25 0 25 50 75100125 temperature (c) charge pump current i pllf ( a) v pllf = 1v current sense amplifier input bias current vs temperature (non-inverting pin) -0.60 -0.55 -0.50 -0.45 -0.40 -50 -25 0 25 50 75 100 125 temperature (c) current sense amplifier input bias current ( a) v cc = 8v, v cs1 (-) = v cs2 (-) = 0v sync/shdn input voltage vs temperature 0.9 1.0 1.1 1.2 1.3 1.4 1.5 -50 -25 0 25 50 75 100 125 temperature (c) sync/shdn input high voltage (v) sync/shdn input high sync/shdn input low
14 ? 2006 semtech corp. www.semtech.com power management sc2441a typical characteristics v in start-up threshold voltage vs temperature 1.70 1.71 1.72 1.73 1.74 1.75 -50-25 0 25 50 75100125 temperature (c) v in start-up threshold voltage (v) v in hysteresis voltage vs temperature 0.075 0.080 0.085 0.090 0.095 0.100 0.105 0.110 -50 -25 0 25 50 75 100 125 temperature (c) v in hysteresis voltage (v) overload hiccup threshold vs temperature 0.350 0.355 0.360 0.365 0.370 0.375 0.380 0.385 0.390 0.395 0.400 -50 -25 0 25 50 75 100 125 temperature (c) overload hiccup threshold (v) v ss1,2 = 3.5v soft-start voltage threshold (to enable overload hiccup protection) vs temperature 3.0 3.2 3.4 3.6 3.8 4.0 -50 -25 0 25 50 75 100 125 temperature (c) soft-start voltage threshold (to enable overload hiccup protection) (v) soft-start discharge current vs temperature 7.0 7.5 8.0 8.5 9.0 -50 -25 0 25 50 75 100 125 temperature (c) soft-start discharge current ( a) v fb1 =v fb2 =0.3v, v ss1 =v ss2 =3v soft-start voltage (to restart overload shutdown) vs temperature 0.50 0.52 0.54 0.56 0.58 0.60 -50-25 0 255075100125 temperature (c) soft-start voltage (to restart overload shutdown) (v) soft-start disable voltage vs temperature 0.75 0.77 0.79 0.81 0.83 -50 -25 0 25 50 75 100 125 temperature (c) soft-start voltage (to restart overload shutdown) (v) v fb1 =v fb2 =0.45v, v comp1 =v comp2 =2v soft-start threshold voltage (to eable pwm operation) vs temperature 1.20 1.22 1.24 1.26 1.28 1.30 -50 -25 0 25 50 75 100 125 temperature (c) soft-start threshold voltage (to eable pwm operation) (v) v fb1 =v fb2 =0.03v current sense amplifier input bias current vs temperature (inverting pin) -40 -35 -30 -25 -50 -25 0 25 50 75 100 125 temperature (c) current sense amplifier input bias current ( a) v cc = 8v, v cs1 (-) = v cs2 (-) = 0v
15 2006 semtech corp. www.semtech.com power management sc2441a typical characteristics boost section feedback pin bias current vs temperature 25 30 35 40 45 50 55 60 65 -50 -25 0 25 50 75 100 125 temperature (c) boost section feedback pin bias current (na) boost section amplifier transconductance vs temperature 55 65 75 85 95 105 -50 -25 0 25 50 75 100 125 temperature (c) boost section amplifier transconductance ( ) boost section amplifier open loop gain vs temperature 50 51 52 53 54 55 56 -50 -25 0 25 50 75 100 125 temperature (c) boost section amplifier open loop gain (db) boost section switch saturation voltage vs temperature 0.25 0.27 0.29 0.31 0.33 0.35 -50 -25 0 25 50 75 100 125 temperature (c) boost section switch saturation voltage (v) i sw = 0.6a boost section switch current limit vs temperature 0.60 0.65 0.70 0.75 0.80 0.85 0.90 -50 -25 0 25 50 75 100 125 temperature (c) boost section switch current limit (a) boost section feedback voltage vs temperature 1.20 1.22 1.24 1.26 1.28 -50-250 255075100125 temperature (c) boost section reference voltage (v) 1.8v < v in < 16.5v bottom gate driver transition time vs load capacitance 0 20 40 60 80 100 0110 load capacitance (nf) transition time (ns) v cc = 12v t r t f 25c bottom gate driver transition time vs load capacitance 0 20 40 60 80 100 0110 load capacitance (nf) transition time (ns) v cc = 5v t r t f 25c
16 2006 semtech corp. www.semtech.com power management sc2441a typical characteristics phase shift vs temperature 0 45 90 135 180 225 -50 -25 0 25 50 75 100 125 temperature (c) phase (deg) r osc = 66.5k r 2 = 31.6k r 2 = 41.2k r 2 = 61.9k r 2 = 121k f sync = 300khz phase shift vs temperature 0 45 90 135 180 225 -50 -25 0 25 50 75 100 125 temperature (c) phase (deg) r osc = 40.2k r 2 = 36.5k r 2 = 47.5k r 2 = 71.5k r 2 = 143k f sync = 500khz phase shift vs temperature 0 45 90 135 180 225 -50-25 0 255075100125 temperature (c) phase (deg) f sync = 400khz r 2 = 34.8k r 2 = 46.4k r 2 = 68.1k r 2 = 140k r osc = 51.1k upper gate driver transition time vs load capacitance 0 20 40 60 80 100 0110 load capacitance (nf) transition time (ns) v cc = 12v t r t f 25c upper gate driver transition time vs load capacitance 0 20 40 60 80 100 0110 load capacitance (nf) transition time (ns) v cc = 5v t r t f 25c percentage deviation in phase shift vs temperature -25 -20 -15 -10 -5 0 5 10 15 20 25 -50 -25 0 25 50 75 100 125 temperature (c) phase deviation (%) r osc = 40.2k r 2 = 36.5k r 2 = 47.5k r 2 = 71.5k r 2 = 143k f sync = 500khz percentage deviation in phase shift vs temperature -60 -50 -40 -30 -20 -10 0 10 20 30 -50 -25 0 25 50 75 100 125 temperature (c) phase deviation (%) r osc = 66.5k r 2 = 31.6k r 2 = 41.2k r 2 = 61.9k r 2 = 121k f sync = 300khz percentage deviation in phase shift vs temperature -20 -10 0 10 20 -50-250 255075100125 temperature (c) phase deviation (%) f sync = 400khz r osc = 51.1k r 2 = 34.8k r 2 = 46.4k r 2 = 68.1k r 2 = 140k
17 ? 2006 semtech corp. www.semtech.com power management sc2441a overview the sc2441a is a constant-frequency switching regulator capable of operating from 1.8v to 20v input. it consists of two current-mode step-down switch-mode pwm controllers driving all n-channel mosfets and an auxiliary step-up current-mode converter with an integrated 0.6a power switch. a local supply (>5v) can be generated from a low voltage input (3.3v, 2.5v or 1.8v) to provide sufficient gate drives for the step-down converters. ? the two step-down channels of the sc2441a operate at 180 degrees out of phase from each other. input currents are interleaved in a two-phase converter so input ripple current is lower and lower input capacitance can be used for filtering. ? the step-down controllers of the sc2441a operate in synchronous continuous-conduction mode. they can function either as two independent step-down controllers producing two separate outputs or as a dual-phase single- output controller by tying the fb2 pin to v in (figure 2). in single output mode, the channel 1 error amplifier controls both channels and the channel 2 error amplifier is disabled. soft-start and overload hiccup of both channels are also controlled by channel 1. in figure 2 the output sel of the comparator a1 determines which error amplifier outputs and fault signals are routed to channel 2. the minimum required fb2 voltage for single output mode is 1.55v. phase-locked loop and synchronization ? the sc2441a utilizes a phase-locked oscillator (figure 5) for clock generation and external synchronization. the advantages of using a phase-locked loop (pll) are: (i) when the step-down channels are synchronized, the auxiliary step- up regulator in the sc2441a can be made to run at twice the external clock frequency to reduce component size and (ii) two or more sc2441a can be daisy chained using the clock output (pin 28) and interleaved with programmable phase shift. each step-down controller within a sc2441a operates at 180 degrees out of phase from the other step- down controller. the switching frequency of the step-down controllers can be set with an external resistor rosc. the boost regulator and the step-down controllers are capable of operating up to 2 mhz and 1 mhz respectively. it is necessary to consider the operating duty-ratio range before deciding the switching frequency. see applications information section for more details. ? consider the detailed block diagram of the pll in figure 5. the phase/frequency detector compares the buffered external clock xclk with the t q output of the toggle flip- flop. if the rising edge of xclk leads that of t q , then q u will go high between the two corresponding rising edges. switch s 1 is closed, charge is delivered to the loop filter and the voltage at the pllf pin increases. this in turn causes the current output of the voltage to current converter (v/i) and the switching frequency of the current-controlled oscillator (cco) to increase. if t q rises before xclk, then q d will go high from the rising edge of t q to the rising edge of xclk. switch s 2 is closed, charge is drawn from the loop filter and the pllf voltage falls. the switching frequency of the current-controlled oscillator (cco) decreases. when the pll is in lock, the rising edges of xclk and t q are aligned. q u and q d will go high for only a few gate delays. the pllf stabilizes to a constant dc voltage and the cco runs at the same frequency as the external clock. ? in the absence of an external clock, s 2 is closed and the pll loop filter is continuously discharged. not shown in figure 5 is an internal pllf lower clamp circuit that limits the minimum voltage at the pllf pin to 0.17v. this sets the lowest operating frequency and thus the lower bound of the pll lock-range. the v/i in figure 5 is shown with two non-inverting inputs. the lower voltage non-inverting input takes control of the v/i. if the pllf pin is tied to vin (>1.8v) through a current-limiting resistor, then the 0.4v input of the v/i will predominate. the 0.4v input therefore sets the upper excursion limit of the v/i and the maximum operating frequency of the pll at a given rosc. the maximum pll frequency to the minimum locking frequency ratio is about 2. when the sc2441a is not synchronized externally, the pllf pin should be tied high through a resistor. the cco will then run at its maximum frequency. ? when two sc2441as are used in a master-slave configuration, the pllf pin of the master sc2441a is tied high and its free running frequency is set with the resistor rosc. ckout of the master is then tied to the shdn sync/ input of the slave sc2441a. the free running and the operation
18 ? 2006 semtech corp. www.semtech.com power management sc2441a minimum locking frequencies of the slave should be selected to accommodate the variation in the master ? s frequency. phase shift between the master and the slave can be programmed with an optional resistor (figure 5). more detailed discussion can be found in the application information. pulling the shdn sync/ pin below 0.5v shuts off the sc2441a after 85 s time delay. control loop ? the step-down controllers and the boost regulator in the sc2441a use peak current-mode control for fast transient response and current sharing in single output operation. current-mode switching regulators utilize a dual-loop feedback control system. the error amplifier output controls the peak inductor current of that channel. this is the inner current loop. the double reactive poles of the output lc filter are reduced to a single real pole by the inner current loop, easing loop compensation. fast transient response can be obtained with a simple type-2 compensation network. in the outer loop, the error amplifier regulates the output voltage. ? referring to the block diagrams in figures 2 and 3, the sensed inductor current is summed with the slope- compensating ramp before compared to the output of the error amplifier. the pwm comparator trip point determines the switch turn-on pulse width. the current-limit comparator ilim turns off the power switch when the sensed current exceeds the corresponding current-limit threshold. ilim therefore provides cycle-by-cycle current limit. ? all three converters in the sc2441a have internal ramp- compensation to prevent sub-harmonic oscillation when operating above 50% duty cycle. the internal compensating ramp is designed for an inductor ripple-current between 4 1 and of the maximum inductor current and the peak- to-peak current-sense voltage (csp-csn of the step-down controllers) between and of the current-limit threshold (25mv). the current-limits of all three converters are unaffected by the compensation ramps. current-sensing ? the inductor current needs to be sensed for use as pwm modulating ramp. either sense resistor or inductor series resistance (dcr) can be used as the sensing element for the step-down controllers. since the maximum current- sense voltage (csp-csn) is only 25mv, a precision sense resistor in series with the inductor can be used at the output without resulting in excessive power dissipation. alternatively the dcr of the inductor can also be used. both methods are less sensitive to supply and ground transients than high-side or low-side sensing because the sensed voltage is developed at the output of the step- down converter. dcr sensing will be described in more details in the applications information section. ? boost switch current is sensed with an integrated sense resistor with a minimum current-limit of 0.6a. error amplifiers all error amplifiers in the sc2441a are of transconductance type. converters are compensated with series rc network from the comp pins to the ground. an additional small parallel capacitor may be required for stability. in figure 2 the error amplifiers ea1 and ea2 are shown with two non-inverting inputs. the non-inverting input with lower voltage predominates. one positive input is biased to a 0.5v precision reference. the other non-inverting input of the error amplifier is tied to a voltage equal to (v ss/en - 1.25v)/3. during converter start up, the effective positive input of the error amplifier stays at 0 until the soft-start capacitor at the ss/en pin is charged above 1.25v. the corresponding comp pin is also pulled low by the comparator a 2 or a 3 . after the ss/en voltage exceeds 1.25v, the comp pin is released. both the upper and the lower gate drives remain low until the comp voltage exceeds 1.85v. if the soft-start capacitor charging time is sufficiently long, then both the fb and the output voltage will track the divided ss/en voltage on their way to regulation. if the starting output voltage is non-zero, then the comp voltage and the corresponding gate drives will remain low until the divided ss/en voltage exceeds the feedback voltage. starting into a pre-existing output is seamless. operation (cont.)
19 ? 2006 semtech corp. www.semtech.com power management sc2441a operation (cont.) in closed loop operation, ea1 and ea2 output voltage vary from 1.2v to 3.5v with the range 1.2v to 1.85v corresponding to negative peak sense voltages. both gate drives are kept off until the comp voltage exceeds 1.85v in start up. the error amplifier of the step-up converter has a 1.25v reference voltage. its output voltage excursion is from 0.8v to 1v in closed-loop operation. current-limit the 25mv maximum current sense voltage is the cycle-by- cycle peak current limit of the step-down controller. gate drivers the sc2441a uses an adaptive non-overlapping control scheme to switch the upper and the synchronous mosfets. the synchronous mosfet of each step-down channel is turned off at the falling-edge of the phase clock. the control (upper) mosfet is not turned on until the synchronous gate drive goes low. the phase inductor current ramps up. when the sensed inductor current reaches the threshold determined by the error amplifier output and ramp compensation, the control mosfet is turned off. the synchronous mosfet is not turned on until the upper gate drive goes low. the supply voltage for the upper gate driver is obtained from a diode-capacitor bootstrap circuit. if the bootstrap capacitor is charged from v cc , then the high-side gate drive voltage will swing from approximately 2v cc to ground. the synchronous gate drive swings from v cc to ground. soft-start and overload protection figure 4 shows the functional diagram of the soft-start and overload protection circuit. the soft-start capacitor c ss and its charging resistor r ss are tied to the ss/en pin. together they set the soft-start time. before v cc rises to 4.5v, the undervoltage lockout circuit discharges c ss to ground. after v cc rises above 4.5v, q 1 turns off and c ss is slowly charged by r ss . comparator c 2 and latch l 2 first disable both the upper and lower gate drives. hysteretic comparator c 1 resets the latch l 1 so that hiccup is disabled during start up. as mentioned above, there is no pwm (=tgon) pulse until c ss is above 1.25v and the corresponding comp rises above 1.85v. once the first tgon pulse appears, l 2 is reset and both gate drivers of that channel are enabled. after c ss is charged above 3.3v, c 1 output goes low. hiccup is armed. if the output voltage is less than 70% of the set value due to improper start up or output overload, then c 3 will set the overload latch l 1 . both gate drivers of the channel are turned off and the 10 a current source discharges c ss . r ss must be large enough to ensure full discharge of c ss down to 0.5v. soft-start process should be slow enough to allow the output to reach 70% of its final value before hiccup is armed. the overload latch l 1 is reset when the c ss capacitor is discharged below 0.5v. the 10 a current source turns off. c ss capacitor is recharged by r ss and the converter undergoes soft-start. if overload persists, the step-down converters will undergo repetitive shutdown and restart (hiccup). if the output is short-circuited, the inductor current will not increase indefinitely between the times the inductor current reaching its current limit and shutdown. this is due to cycle skipping reduces the actual operating frequency. pulling the ss/en pin below 0.8v with an open-collector transistor sets the disable latch l 2 and turns off the gate drives. the ss/en pin can be used as the enable input for the controller. the soft start timing diagram and the hiccup operation timing diagram are shown in figures 6a and 6b respectively.
20 ? 2006 semtech corp. www.semtech.com power management sc2441a operating frequency (f s ) the switching frequency in the sc2441a is user- programmable. the advantages of constant frequency operation are simple passive component selection and fast transient response with simple frequency compensation. before setting the operating frequency, the following trade-offs should be considered. 1) passive component sizes 2) converter efficiency 3) emi 4) minimum switch on time and 5) maximum duty ratio for a given output power, the sizes of the passive components are inversely proportional to the switching frequency, whereas mosfet?s/diodes switching losses are proportional to the operating frequency. other issues such as heat dissipation, packaging and the cost issues should be considered. the frequency bands for signal transmission should be avoided because of em interference. the switching frequency of both step-down controllers is set with an external resistor from pin 10 to the signal ground. the set frequency is inversely proportional to the resistor value (figure 7) and can be approximated as: 1.22 sw osc f 101618 r r osc is in k ? and f sw is in khz. the internal oscillator starts to operate once v in exceeds its uvlo threshold. the oscillator output, clk, (see figure 2) clocks the step-up converter. the frequency divider generates two out-of-phase clocks, clk1 and clk2, at a half of clk frequency. clk1 and clk2 clock the step- down channels. the switching frequency of the step-up converter is twice those of the step-down controllers. if both step-down channels are running at 250khz, then the boost section will be running at 500khz. applications information rosc vs single channel switching frequency 10 30 50 70 90 110 130 150 100 300 500 700 900 1100 switching frequency (khz) r osc (k ) figure 7. r osc vs. step-down channel free-running frequency minimum switch on time limitation in both step-down controllers, the falling edge of the clock turns on the top mosfet. the inductor current ramps up so does the sensed voltage. after the sensed voltage crosses a threshold determined by the error amplifier output, the top mosfet is turned off. the propagation delay time from the turn-on of the controlling fet to its turn-off is the minimum switch on time. the sc2441a has a minimum on time of about 180ns at room temperature. this is the shortest on interval of the controlling fet. the controller either does not turn on the top mosfet at all or turns it on for at least 180ns. for a synchronous step-down converter, the operating duty cycle is v o /v in . so the required on time for the top mosfet is v o /(v in f s ). if the frequency is set such that the required pulse width is less than 180ns, then the converter will start skipping cycles. due to minimum on time limitation, simultaneously operating at very high r osc vs. step-down channel switching frequency
21 ? 2006 semtech corp. www.semtech.com power management sc2441a switching frequency and very short duty cycle is not practical. if the input voltage is 3.3v and the operating frequency is 1mhz, the lowest output voltage will be 0.6v. there will not be enough modulation headroom if the on time is simply made equal to the minimum on time of the sc2441a. for ease of control, we recommend that the required pulse width be at least 1.5 times the minimum on time. maximum duty-cycle consideration the top mosfet turns off for at least 200ns every cycle regardless of the switching frequency. this places an upper bound on the voltage conversion ratio at a given switching frequency. if the desired output voltage requires high operating duty- cycle, then operating frequency will have to be lowered to allow modulating headroom. rc filtering network for v cc and v in pins a rc filtering network is recommended for the sc2441a v cc and v in pin connections. as shown in figure 1, r 6 plus c 8 and r 2 plus c 2 are the filtering networks for v cc pin and v in pin respectively. the value of the r 6 and r 2 ranges from 3.3 ? to 5.11 ?. c 8 and c 2 should be larger than 1 f . c 8 and c 2 are the decoupling capacitors for the v cc pin and v in pin. they should be placed as close as possible to the pins of the sc2441a to achieve the best decoupling performance. due to the different functionalities of the v cc pin and v in pin, c 2 should be placed between the v in pin and the signal ground of the sc2441a. and c 8 should be placed between the v cc pin and the power ground of the sc2441a. the recommended connections for the v cc pin and v in pin are illustrated in figure 8. v in gnd pgnd1 sc2441a 9 24 v cc 1 21 c 2 c 8 r 2 r 6 figure 8. rc network connections for v in and v cc pins step-up converter the sc2441a features a step-up regulator and two step- down controllers. the boost section of the sc2441a comprises of pins 7, 8, 26 and 27. pin 26 is the independent power ground for the boost converter section, which should be separated from the step-down section power ground pin 24 in layout to minimize the noise influence. the boost section in sc2441a has an internal reference set at 1.25v. the output of the boost section can be programmed with external resistors r 1 and r 4 as shown in figure 1. 4 4 1 boost r r r 1.25v v sc2441a utilizes a transconductance error amplifier for the step-up controller and it can be compensated with c 3 , r 5 and c 5 as shown in figure 1. the step-up controller in the sc2441a employs cycle-by-cycle peak current limit to protect the internal switching transistor. current limit threshold is typically 0.8a. in the applications where only low input voltage is available, the step-up converter in the sc2441a is very useful for generating an auxiliary output to power the gate drive of the step-down controllers. applications information
22 ? 2006 semtech corp. www.semtech.com power management sc2441a assuming that the efficiency of the boost converter is and the boost converter is running in ccm with duty ratio d. the peak inductor current is the saturation current rating of the selected inductor should be at least 1.2 times of the calculated peak current value. step-up converter capacitor selection input capacitor : : : : : the input capacitance should be large such that the input transients due to both the step-up and the step-down converters do not trip the uvlo threshold 1.71v. since the sc2441a controls a 2-phase low input voltage step-down converter, the input capacitance is sized to handle the input ripple current of the buck converter. this is usually sufficient for the auxiliary boost converter because the input current in a boost converter is continuous. output capacitor: unlike buck converter, pulse current is delivered to the output of a boost converter. to reduce the output ripple voltage, low esr capacitors should be used. the output capacitor should also be able handle the output ripple current. the sc2441a is designed to use multi-layer ceramic capacitor as the sole output capacitor. maximum output current of the step-up converter figure 3 shows that the boost switch current is sensed with an internal sense resistor rs and it is internally limited at 0.6a. so the maximum output current can be given as ( is the efficiency of the step-up section): o3 in 3 max o3, v v 2 0.6a i ) ( sw3 pgnd2 sc2441a 27 26 l 1 d 1 c 1 c 2 r 1 v cc pgnd1 v in 21 24 small loop figure 9. step-up section layout illustration as shown in figure 9, to minimize the switching noise generated by the step-up converter, the loop formed by d 1 , c 1 , sw3 and pgnd2 should be as small as possible. and the pgnd2 pin should be tied to pgnd1 at one spot close to the pgnd1 pin. step-up converter inductor selection for a specified inductor current ripple ratio 3 (peak-to- peak current ripple v.s. actual input current i in ), the inductor value is . v v ) v v 1 ( i f v l 3 o in 3 o in 3 o 3 3 s in 1 typically, select 3 <2 for a continous conduction mode (ccm) operation. if v in = 3.3v, v o3 = 5v and i o3 = 100ma with 3 = 1.6 and f s3 = 1mhz, then, l 1 = 4.7 h. applications information 2 1 t d l v v i v i 1 in in o3 o3 l1peak
23 ? 2006 semtech corp. www.semtech.com power management sc2441a loop compensation for the step-up converter a simple small signal model for current-mode boost converter in continuous-conduction mode is shown in figure 10. figure 10. small signal model of boost converter. in figure 10, c o3 and r esr3 are the capacitance and the esr of the output capacitor, g m3 is the error amplifier transconductance and k 3 is the current loop gain. if one specifies the loop crossover frequency f c , the compensation component values are readily calculated as , r 5 . 0 r r f 2 1 | f f 1 | 2 r ) d 1 ( k g h c 3 o 3 esr 3 esr c 1 z c 3 o 3 3 3 m 3 4 ) 2 r r ( c c 1 r 3 o 3 esr 3 o 4 4 and 3 o 3 esr 4 5 r r 2 c c . l 2 r ) d 1 ( f 3 3 o 2 3 1 z b a b 3 r r r h soft-starting the step-down controllers the soft-start of the two step-down converters are independently controlled through ss1 pin and ss2 pin. as lillustrated in figure 4, if v cc is below 4.5v, q 1 will be on, keeping c ss discharged. when fault goes low, q 1 is turned off, c ss gets charged via r ss from v cc . values of r ss and c ss set different start-up times. as shown in figure 4, if the output falls below 70% of its setpoint, the css will be discharged with a 10 a current sink. r ss must be large enough to allow the soft-start capacitor to be discharged below 0.5v. soft-start process should be long enough to allow the output to reach 70% of its final value before hiccup is armed. coincident soft-start the step-down controllers can be made to start coincidently. the method is shown in figure 11. ss1/en1 sc2441a 3 ss2/en2 17 r ss1 c ss1 r ss2 c ss2 v cc v cc d 1 d 2 c ss figure 11. coincident soft-start for step-down converters the capacitance of c ss , as shown above, should be more than 3 times of the capacitance of the c ss1 and c ss2 . applications information b a
24 ? 2006 semtech corp. www.semtech.com power management sc2441a dcr current sensing either precision sense resistor or inductor dcr can be used as the inductor current sensing element. figure 12. current sensing circuit. in figure 12 sw1 and sw2 represent the mosfet switches. cs is the current sense amplifier. i cs+ and i cs- are the input bias currents of the cs. l 1 is the output inductor. r 1 is the dc resistance of l 1 . r 2 , r 3 and c 1 constitute the dcr current sensing network. assuming that cs input bias currents are zero and that r 3 is not used, if the time constant l 1 /r 1 is made equal to the time constant r 2 c 1 , then the voltage across the inductor dcr, r 1 , will be replicated across c 1 in the steady state (see figure 13). the following equations apply: /2 i i i 1 l o peak l1 . /2 i i i 1 l o valley l1 . 1 l1 c1 r (t) i (t) v where, i o is the output current and 1 l i is the peak-to- peak l 1 current ripple. the inductor current can therefore be sensed by monitoring c 1 voltage. l should be selected so that the is between 25% to 33% of the i o . however cs input bias currents are not zero. i cs+ and i cs- are typically 0.4 a and 40 a respectively (see electrical characteristics) and can not be ignored. figure 13. voltage waveform c 1 and r 1 in figure 12, r 2 and r 3 resistive divider attenuates the sensed signals when i . the time constant resulting from l 1 and its dcr r 1 is: define r equ : the time constant of the dcr sensing network is: if c1 = l1 , then the peak and valley voltages across c 1 will be:

2 i r r r r r i v o 3 2 1 3 equ cs valley c1 l1 i ) ( i cs+ therefore introduces an offset error to the sensed voltage. to reduce this error, r equ must be minimized. suppose v in =5v; v out =2.5v; d=50%; i out =20a; f sw =500khz; l 1 =0.5 h; r 1 =2m ?; i cs+ =1 a. the output current limit is set at 28a. the time constant formed by l 1 and r 1 is 1 1 1 l1 c 3 r 2 r 3 r 2 r 0.25ms r l 5a i 1 l 25mv i 28a l1

2 r r r r r i v 3 2 1 3 equ cs peak c1 ) ( 0t voltage drop on r 1 --- i l1 (t)r 1 voltage on c 1 --- v c1 (t) v v c1.peak v c1.valley r 1 i l1.peak r 1 i l1.valley r 1 i o applications information sc2441a sw1 sw2 l 1 r 1 r 2 c 1 r 3 + - cs + v c1 - c out r load v in i cs+ i cs-
25 ? 2006 semtech corp. www.semtech.com power management sc2441a pre-biased start up sometimes the step-down converter is to start into a pre-biased output load. the pre-biased voltage is normally lower than the output setpoint of the step-down converter. as described earlier, pre-bias startup process with the sc2441a is seamless. the testing setup of the pre-biased start-up is shown as in figure 14. d1 v s blocking diode external voltage source module under test + - r load v o figure 14. test setup for pre-biased start up applications information in figure 14, v s is the external power supply pre-biasing v o . d 1 blocks the output of the power module under test from v s during soft-start. r load is the resistive load of the module under test. before power-up the module, monitor v o to ensure that it is the desired pre-biased output voltage. then power-up the module. v o should rise smoothly. free-running operation the internal oscillator of the sc2441a can either free- run or it can be phase-locked to an external clock. in free-running mode, the internal phase-locked loop is disabled by tying an external resistor from the pllf pin to v in . the external resistor rosc (see figure 5(a)) programs the channel frequency. the pllf pull-up resistor should be carefully selected so that the voltage at the pllf pin is above 1v. a value between 20k ? to 50k ? is recommended. pull-up resistor can also be tied to v cc if v cc is present before the sc2441a starts to switch. the advantage tying the pull-up resistor to v cc is because that the v cc is a regulated output from either a boost converter or a sepic converter. the resistor from the pllf pin can be tied to v cc if v cc is from a boost converter output. the reason is that the v cc will be powered up from the input v in before output of the boost converter reaches the setpoint. however, in some applications, a sepic converter is employed to get stable v cc due to the wide input voltage range. in this case, the resistor from the pllf pin should not be connected to the v cc due to the presence of a dc blocking capacitor in the converter. the sc2441a will not switch if the pllf pin is at zero volt. applying more than 2.1v at the pllf pin activates the diode clamp circuit (see figure 5(a)). the filtering components (r 1 ,r 2 , c 1 and c 2 in figure 5(a)) are not needed while free-running. the clamp activation will have no effect on the pll if v pllf >1v. the internal clock is brought out to the ckout pin. the signal at ckout pin can be used as the synchronizing clock for other sc2441as in a master-slave configuration. 0.25ms c 3 r 2 r 3 r 2 r 1 25mv 5a 28a 2 r r r r r r r r a 1 3 2 1 3 3 2 2 3 ) ( ) ( with an arbitrary selection of 3.01k 3 r 2 r 3 r 2 r , we can get c 1 =83nf. since 83nf is not a standard capacitance value, we use 100nf capacitor for c 1 . consequently, k 3 r 2 r 3 r 2 r 2.5 . and we can also derive: 25mv 5a 28a

2 2.5k r r 2.5k a 1 2 1 6.80k 2 r 3.92k 3 r
26 ? 2006 semtech corp. www.semtech.com power management sc2441a as shown in figure 15, the ckout signal of the master sc2441a is the input sync signal for the slave sc2441a. the r 1 , c 1 and c 2 constitute the filtering circuit stabilizing the phase lock loop in the slave sc2441a. r2 (between 30k ? and 150k ?) determines the phase shift between the slave ckout and its sync input. pll frequency compensation applying synchronizing clock with step change in frequency adjust compensation components until overshoot and ringing at pllf pin is minimized. output inductor and ripple current in step-down sections both step-down controllers in the sc2441a operate in synchronous continuous-conduction mode (ccm) regardless of the output load. the output inductor selection/design is based on the output dc and transient requirements. both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor current during load transients. conversely smaller inductors results in lower dc copper losses but the ac core losses (flux swing) and the winding ac resistance losses are higher. a compromise is to choose the inductance such that the peak to peak inductor ripple current is 20% to 30% of the rated output current. assume that the inductor current ripple (peak-to-peak) is ? then the inductance will be the peak current in the inductor becomes (1+ /2)*io and the rms current is . 12 1 i i 2 o rms , l the followings are to be considered when choosing inductors. a) inductor core material: for high efficiency applications above 350khz, ferrite, kool-mu and polypermalloy materials should be used. low-cost powdered iron cores can be used for cost sensitive-applications below 350khz but with attendant higher core losses. master - slave mode configuration the configuration for sc2441a master-slave mode operation is shown in figure 15. the master is made free running, the master clock frequency should be within the synchronizing range of the slave. in the master-slave mode, the ss2441a can be synchronized to an external clock signal applied to the sync pin. external filtering componets (r 1 , r 2 , c 1 and c 2 ) on the pllf pin are necessary for the slave sc2441a . the pllf pull-up resistor is not necessary for the slave converter. phase shift between the master and the slave is the phase lag measured between the sync input and the clock output of the slave. typical relationship between the phase shift and the slave value of the resistor r 2 is shown in the ?typical characteristics?. for the sc2441a running at slave mode, its free-runing frequency (internal switching frequency) set with rosc should be programmed 20% higher than the external synchronization frequency. figure 15. master-slave synchronization applications information . f i ) d 1 ( v l s o o pllf sync ckout pllf sync ckout master sc2441a slave sc2441a r4 r3 r2 r1 c2 c1 vin
27 ? 2006 semtech corp. www.semtech.com power management sc2441a b) select inductance value: sometimes the calculated inductance value is not available off-the-shelf. the designer can choose the adjacent (larger) standard inductance value. the inductance varies with temperature and dc current. it is a good engineering practice to re-evaluate the resultant current ripple at the rated dc output current. c) current rating: the saturation current of the inductor should be at least 1.5 times of the peak inductor current under all conditions. output capacitor (c o ) and v out ripple in step-down sections the output capacitor provides output current filtering in steady state and serves as a reservoir during load transient. the output capacitor can be modeled as an ideal capacitor in series with its parasitic esr (r esr ) and esl (l esl ) (figure 16). figure 16. c o equivalent circuit if the current through the branch is i b (t), the voltage across the terminals will then be ). t ( i r dt ) t ( di l dt ) t ( i c 1 v ) t ( v b esr t 0 b esl b o o o this basic equation illustrates the effects of esr, esl and c o on the output voltage. the first term is the dc voltage across c o at time t=0. the second term is the ripple-voltage caused by the inductor ripple-current. the third term is the voltage ripple due to esl and the fourth term is the voltage ripple due to esr. the total output voltage ripple is then a vector sum of the last three terms. applications information since the inductor current is a triangular waveform with peak-to-peak value * i o , the ripple-voltage caused by inductor current ripples is . f c 8 i v s o o c the ripple-voltage due to esl is d i f l v o s esl esl and the esr ripple-voltage is . i r v o esr esr aluminum capacitors (e.g. electrolytic, solid os-con, poscap, tantalum) have high capacitances and low esl?s. the esr has the dominant effect on the output ripple voltage. it is therefore very important to minimize the esr. when determining the esr value, both the steady state ripple-voltage and the dynamic load transient need to be considered. to keep the steady state output ripple-voltage < ? v o , the esr should satisfy . i v r o o 1 esr to limit the dynamic output voltage overshoot/ undershoot within (say 3%) of the steady state output voltage) under 0 to full load current swing, the esr value should be . i v r o o 2 esr the required esr value of the output capacitors should be r esr = min{r esr1 ,r esr2 }. in the aluminum capacitor selection, the working voltage rating is normally suggested to be greater than 1.5 v o . the allowable current ripple (rms) should be greater than co lesl resr i b (t)
28 ? 2006 semtech corp. www.semtech.com power management sc2441a 2 b 1 a 1 2 b 1 2 a 1 2 2 b 1 a 1 2 a 1 a 1 2 b 1 b 1 2 b 1 2 a 1 2 b 1 a 1 b 1 a 1 eq ) c c ( c c ) r r ( ) c r c r ( c c ) r r ( r r : ) ( r where r 1a and c 1a are the esr and capacitance of electrolytic capacitors, and r 1b and c 1b are the esr and capacitance of the ceramic capacitors respectively (figure 17). c1a r1a c1b r1b ceq req figure 17. equivalent rc branch. r eq and c eq are both functions of frequency. for rigorous design, the equivalent esr should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. if r 1a = r 1b = r 1 and c 1a = c 1b = c 1 , then r eq and c eq will be frequency- independent and r eq = 1/2 r 1 and c eq = 2c 1 . input capacitor (c in ) in step-down sections the input supply to the converter usually comes from a pre-regulator. since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. a simple buck converter is shown in figure 18. figure 18. buck converter input model as shown in fig. 18, the internal dc input voltage source applications information . 3 2 i o usually it is necessary to have several capacitors of the same type in parallel to satisfy the esr requirement. the voltage ripple cause by the capacitor charge/ discharge should be an order of magnitude smaller than the voltage ripple caused by the esr. to guarantee this, the capacitance should satisfy . r f 2 10 c esr s o in many application circuits, several low esr ceramic capacitors are added in parallel with the aluminum capacitors to further reduce esr and improve high frequency decoupling. since the capacitances and the esr?s of ceramic and aluminum capacitors are different, the following remarks are made to clarify some practical issues. remark 1: high frequency ceramic capacitors may not carry most of the ripple current. it also depends on the capacitor value. only when the capacitor value is set properly, the effect of ceramic capacitor low esr starts to be significant. for example, if a 10 f, 4m ? ceramic capacitor is connected in parallel with 2x1500 f, 90m ? electrolytic capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors at the ripple frequency. if a 100 f, 2m ? ceramic capacitor is used, the ripple current in the ceramic capacitor will be about 4.2 times of that in the electrolytic capacitors. when two 100 f, 2m ? ceramic capacitors are used, the current ratio increases to 8.3. in this case most of the ripple current flows in the ceramic decoupling capacitor. the esr of the ceramic capacitors will then determine the output ripple-voltage. remark 2: the total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. the total equivalent esr is not simply the parallel combination of all the individual esr?s either. instead they should be calculated using the following formulae. ) c c ( c c ) c r c r ( ) c c ( c c ) r r ( : ) ( c b 1 a 1 b 1 a 1 2 b 1 2 b 1 a 1 2 a 1 2 b 1 a 1 2 b 1 2 a 1 2 2 b 1 a 1 eq
29 ? 2006 semtech corp. www.semtech.com power management sc2441a applications information impedance is r in and the input capacitor c in has an esr denoted as r esr . mosfet and input capacitor current waveforms, esr voltage ripple and input voltage ripple are shown in figure 19. figure 19. typical waveforms at the input of a buck converter. it can be seen that the current in the input capacitor pulses with high di/dt. capacitors with low esl should be used. it is also important to place the input capacitor close to the mosfet?s on the pc board to reduce trace inductances around the pulse current loop. the rms value of the capacitor current is approximately ]. ) d 1 ( d ) d 1 )( 12 1 [( d i i 2 2 2 o cin the power losses at the input capacitors is then p cin = i cin 2 r esr . for reliable operation , the maximum power dissipation in the capacitors should not result in more than 10 o c of temperature rise. many manufacturers specify the maximum allowable ripple current (arms) rating of the capacitor at a given ripple frequency and ambient temperature. the input capacitance should be high enough to handle the ripple current. for higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. at full load, the peak-to-peak input voltage ripple due to the esr is . i ) 2 1 ( r v o esr esr the peak-to-peak input voltage ripple due to the capacitor is . f c di v s in o c from these two expressions, c in can be found to meet the input voltage ripple specification. in a multi-phase converter, channel interleaving can be used to reduce ripple. the two step-down channels of the sc2441a operate at 180 degrees from each other. if both step- down channels in the sc2441a are connected in parallel, both the input and the output rms currents will be reduced. ripple cancellation effect of interleaving allows the use of smaller input capacitors. when converter outputs are connected in parallel and interleaved, smaller inductors and capacitors can be used for each channel. the total output ripple-voltage remains unchanged. smaller inductors speeds up output load transient. when two channels with a common input are interleaved, the total dc input current is simply the sum of the individual dc input currents. the combined input current waveform depends on duty ratio and the output current waveform. assuming that the output current ripple is small, the following formula can be used to estimate the rms value of the ripple current in the input capacitor. let the duty ratios and output currents of channel 1 and channel 2 be d 1 , d 2 and i o1 , i o2 respectively. if d 1 <0.5 and d 2 <0.5, then . i d i d i 2 2 o 2 2 1 o 1 cin if d 1 >0.5 and (d 1 -0.5) < d 2 <0.5, then . i ) 5 . 0 d d ( ) i i )( 5 . 0 d ( i 5 . 0 i 2 2 o 1 2 2 2 o 1 o 1 2 1 o cin if d 1 >0.5 and d 2 < (d 1 -0.5) < 0.5, then . i ) 5 . 0 d d ( ) i i ( d i 5 . 0 i 2 2 o 2 1 2 2 o 1 o 2 2 1 o cin
30 ? 2006 semtech corp. www.semtech.com power management sc2441a the losses in power mosfet?s consist of a) conduction loss due to the channel resistance r ds(on) , b) switching loss due to the switch rise time t r and fall time t f and c) the gate loss due to the gate resistance r g . top switch: the rms value of the top switch current is . ) 1 ( d i i 12 o rms , 1 q 2 its conduction loss is then p tc = i q1,rms 2 r ds(on) . r ds(on) varies with temperature and gate-source voltage. curves showing r ds(on) variations can be found in manufacturers? data sheet. from the si7882dp datasheet, r ds(on) is less than 4.5mohm when v gs is greater than 5v. however r ds(on) increases by nearly 40% as the junction temperature increases from 25c to 125c. the switching losses can be estimated using the simple formula . f v i ) 1 )( t t ( p s in o 2 f r 2 1 ts where t r is the rise time and t f is the fall time of the switching process. to clarify these, we sketch the typical mosfet switching characteristics under clamped inductive mode in figure 21. figure 21. mosfet switching characteristics applications information if d 1 >0.5 and d 2 > 0.5, then . i ) d 1 ( i ) d 1 ( ) i i )( 1 d d ( i 2 2 o 1 2 1 o 2 2 2 o 1 o 2 1 cin power mosfet selection and gate drive main considerations in selecting the mosfet?s are power dissipation, cost and packaging. switching losses and conduction losses of the mosfet?s are directly related to the total gate charge (c g ) and channel on-resistance (r ds(on) ). in order to judge the performance of mosfet?s, the product of the total gate charge and on-resistance is used as a figure of merit (fom). transistors with the same fom follow the same curve in figure 20. 0 5 10 15 20 0 20 40 fom:100*10^{-12} fom:200*10^{-12} fom:500*10^{-12} on-resistance?(mohm) gate?charge?(nc) 50 1 cg 100 rds () cg 200 rds () cg 500 rds () 20 1 rds figure 20. figure of merit curves. the closer the curve is to the origin, the lower is the fom. this means lower switching loss or lower conduction loss or both. it is difficult to find mosfet?s with both low c g and low r ds(on) . usually a trade-off between r ds(on) and c g has to be made. mosfet selection also depends on applications. in many applications, either switching loss or conduction loss dominates for a particular mosfet. for synchronous buck converters with high input to output voltage ratios, the top mosfet is hard switched but conducts with very low duty cycle. the bottom switch conducts at high duty cycle but switches at near zero voltage. for such applications, mosfet?s with low c g are used for the top switch and mosfet?s with low r ds(on) are used for the bottom switch.
31 ? 2006 semtech corp. www.semtech.com power management sc2441a applications information in figure 21, q gs1 is the gate charge needed to bring the gate-to-source voltage v gs to the threshold v gs_th , q gs2 is the additional gate charge required for the switch current to reach its full-scale value i ds . and q gd is the charge needed to charge gate-to-drain (miller) capacitance when v ds is falling. switching losses occur during the time interval [t 1 , t 3 ]. defining t r = t 3 -t 1 . t r can be approximated as . v v r ) q q ( t gsp cc gt gd 2 gs r where r gt is the total resistance from the driver supply rail to the gate of the mosfet. it includes the gate driver internal impedance r gi , external resistance r ge and the gate resistance r g within the mosfet i.e. r gt = r gi +r ge +r g . v gsp is the miller plateau voltage shown in figure 21. similarly an approximate expression for t f is . gsp gt gd gs2 f v )r q (q t only a portion of the total losses p g = q g v cc f s is dissipated in the mosfet package. here q g is the total gate charge specified in the datasheet. the power dissipated within the mosfet package is . f v q r r p s cc g gt g tg the total power loss of the top switch is then p t = p tc +p ts +p tg . if the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. this is because conduction loss is inversely proportional to the input voltage. switching loss however increases with the input voltage. the total power loss of mosfet should be calculated and compared for high-line and low-line cases. the worst case is then used for thermal design. bottom switch: the rms current in bottom switch can be calculated . ) 1 )( d 1 ( i i 12 o rms , 2 q 2 the conduction loss is then p bc =i q2,rms 2 r ds(on) , where r ds(on) is the channel resistance of bottom mosfet. if the input voltage to output voltage ratio is high (e.g. v in =12v, v o =1.5v), the duty ratio d will be small. since the bottom switch conducts with duty ratio (1-d), the corresponding conduction losses can be quite high. due to non-overlapping conduction between the top and the bottom mosfet?s, the internal body diode or the external schottky diode across the drain and source terminals always conducts prior to the turn on of the bottom mosfet. the bottom mosfet switches on with only a diode voltage between its drain and source terminals. the switching loss s d o 2 f r 2 1 bs f v i ) 1 )( t t ( p is negligible due to near zero-voltage switching. the gate loss is estimated as . f v q r r p s cc g gt g bg the total bottom switch loss is then p b =p bc +p bs +p bg . once the power losses p loss for the top (p t ) and bottom (p b ) mosfet?s are known, thermal and package design at component and system level should be done to verify that the maximum die junction temperature (t j,max , usually 125 o c) is not exceeded under the worst-case conditions. the equivalent thermal impedance from junction to ambient ( ja ) should satisfy . p t t loss max , a max , j ja ja depends on the die to substrate bonding, packaging material, the thermal contact surface, thermal compound property, the available effective heat sink area and the air flow condition (free or forced convection). actual temperature measurement of the prototype should be carried out to verify the thermal design. integrated power mosfet drivers there are four internal mosfet drivers in a dual- channel step-down converter.
32 ? 2006 semtech corp. www.semtech.com power management sc2441a once either r o1 or r o2 is chosen, the other can be calculated for the desired output voltage v o . since the number of standard resistance values is limited, the calculated resistance may not be available as a standard value resistor. as a result, there will be a set error in the converter output voltage. this non-random error is the following table lists a few standard resistor combinations for realizing some commonly used output voltages. ) v ( o v 6 . 0 9 . 0 2 . 15 . 1 8 . 15 . 23 . 3 h / ) h - 1 ( 2 . 0 8 . 0 4 . 12 6 . 24 6 . 5 ) m h o ( 1 o r 0 0 2 6 0 8 k 4 . 1k 2 k 1 6 . 2k 2 0 . 4k 2 6 . 5 ) m h o ( 2 o r k 1 k 1 k 1k 1 k 1k 1k 1 only the voltages in boldface can be precisely set with standard 1% resistors. the input bias current of the error amplifier also causes an error in the output voltage. the inverting input bias currents of error amplifiers 1 and 2 are ?60na and ?280na respectively. since the non-inverting input is biased to 0.5v, the percentage error in the second output voltage will be ?100% (0.28 a) r o1 r o2 /[0.5 (r o1 +r o2 )]. to keep this error below 0.2%, r o2 < 4k ? . loop compensation in step-down section the sc2441a uses current-mode control for both step- down channels. current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner current-loop. the higher gain outer loop regulates the output voltage. since the current loop makes the inductor appear as a current source, the complex high-q poles of the output lc networks is split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. this pole-splitting property of current- mode control greatly simplifies loop compensation. applications information using low gate charge mosfets reduces switching loss. it is possible to trade driver ic losses for mosfet switching losses by adjusting the gate resistance. lower gate resistance results in higher gate driving current and faster mosfet switching. however the driver incurs higher losses. conversely higher gate drive resistance limits the gate drive current, thus lowering the driver dissipation. mosfet switching loss is higher. to prevent shoot-through between the top and the bottom mosfets during commutation, one mosfet should be completely turned off before the other is turned on. the sc2441a uses adaptive non-overlapping timing to prevent shoot-through. optimize mosfet driving voltage the on-state dc resistance of a mosfet, r ds_on , is determined by its gate to source voltage. the higher the v gs , the lower the r ds_on will be. once the gate-source voltage exceeds a certain level, the r ds_on becomes relatively constant. there is no benefit except higher dissipation if you further increase the mosfet gate drive voltage. it is recommended to select gate drive voltage (v cc pin) of the sc2441a in between 5v to 7v. setting the output voltage of the step-down section the non-inverting inputs of the error amplifiers are internally biased to 0.5v voltage reference. a simple voltage divider (r o1 at top and r o2 at bottom) sets the converter output voltage. r o2 can be expressed as a function of the voltage feedback gain h=0.5/v o and r o1 . 1 o 2 o r h 1 h r caused by the feedback voltage divider ratio. it cannot be corrected by the feedback loop.
33 ? 2006 semtech corp. www.semtech.com power management sc2441a applications information the inner current-loop is unstable (sub-harmonic oscillation) unless the inductor current up-slope is steeper than the inductor current down-slope. for stable operation above 50% duty-cycle, a compensation ramp is added to the sensed-current. in the sc2441a the compensation ramp is made duty-ratio dependent. the compensation ramp is approximately d 0.734 slope e d 230mv (d) v d is the duty ratio. the slope compensation voltage vs duty ratio is as shown in figure 22. figure 22. slope compensation voltage waveform illustrated as the picture above, as the duty ratio increases, the slope compensation voltage added into the control loop increases too. and the control loop including the slope compensation is shown in figure 23. the voltage transconductance error amplifier (shown in figure 24) has a g m of 315 a/v. c 2 , c 3 and r 2 construct the compensation network for stable operation with optimized load transient response. the feedback gain h and the resistor values are determined using the equations given in the ?setting the output voltage? section with . v 5 . 0 h o slope compensation voltage cs+ cs- + - + + x 29 - + 0.5v fb v be +1.13v + - compensation network comp + - pwm ea figure 23. control flow chart with slope compensation k figure 24. a simple model of current-mode buck converter for the rated output current i o , the first-order gain k is determined as . v i k c o k is the product of equivalent current sensing rs and current amplifier gain gca=29. furthermore the transfer 0.0 0.1 0.2 0.3 0.4 0.5 0.00.20.40.60.81.0 duty ratio (d) slope compensation voltage (v)
34 ? 2006 semtech corp. www.semtech.com power management sc2441a p 2 is a pole for suppressing high-frequency switching noise. so p 2 >> z 2 . to simplify design, one usually assumes that c 3 < 35 ? 2006 semtech corp. www.semtech.com power management sc2441a applications information figure 25. bode plots of the loop response. the resulting crossover frequency is about 49.2khz with phase margin 90 o . if the circuit noise makes the converter jitter, a larger c 3 than the calculated value can be used. effectively the converter bandwidth is reduced to reject high frequency noises. the final circuit should be checked for stability under load transients at different line voltages. the load transient also needs to be measured to ensure that the output voltage is within the specification window. pc board layout issues circuit board layout is very important for the proper operation of high frequency switching power converters. a power ground plane is required to reduce ground bounces. the followings are suggested for proper layout. power stage 1) separate the power ground from the signal ground. in sc2441a the power ground pgnd1 should be tied to the source terminal of lower mosfets. the signal ground agnd should be tied to the negative terminal of the output capacitor (output return terminal). 2) minimize the size of pulse current loop. place the top mosfet, the bottom mosfet and the input capacitors close to each other with short and wide traces. in addition to the aluminum energy storage capacitors, add multi- layer ceramic (mlc) capacitors from the input to the power ground to improve high frequency bypass. 3) reduce high frequency voltage ringing. widen and shorten the drain and source traces of the mosfets to reduce stray inductances. add a small rc snubber if necessary to reduce the high frequency ringing at the phase node. sometimes slowing down the gate drive signal also helps in reducing the high frequency ringing at the phase node. 4) shorten the gate driver path. integrity of the gate drive (voltage level, leading and falling edges) is important for circuit operation and efficiency. short and wide gate drive traces reduce trace inductances. bond wire inductance is about 2~3nh. if the length of the pcb trace from the gate driver to the mosfet gate is 1 inch, the trace inductance will be about 25nh. if the gate drive current is 2a with 10ns rise and falling times, the voltage drops across the bond wire and the pcb trace will be 0.6v and 5v respectively. this may slow down the switching transient of the mosfets. these inductances may also ring with the gate capacitance. 5) put the decoupling capacitor for the gate drive power supplies (bst and vcc) close to the ic and power ground. 10 100 1 10 3 1 10 4 1 10 5 1 10 6 50 0 50 100 73.323 17.588 20 log g vc f ()cf () 310 5 10 f f 10 100 1 10 3 1 10 4 1 10 5 1 10 6 96 94 92 90 90.001 94.713 arg g vc f ()cf () 180 310 5 10 f
36 ? 2006 semtech corp. www.semtech.com power management sc2441a applications information control section 6) the frequency-setting resistor rosc should be placed close to pin 10. trace length from this resistor to the analog ground should be minimized. 7) solder the vcc decoupling capacitor next to the vcc and power ground pgnd pins. 8) place the current-sensing components away from the power circuit and close to the corresponding cs+ and cs- pins. use x7r type ceramic capacitors for current sensing due to their thermal stability. the distance between the two trace should be as close as possible to minize the noise pick-up. 9) use an isolated local ground plane for the controller and tie it to the negative side of output capacitor bank. 10) a large copper area underneath the sc2441a ic is nessary for heat sinking purpose. and multiple layers of large copper area connected through vias can be used for better thermal performance. the size of the vias as the connection between multiple layers should not be too large or solder may seep through the big vias to the the bottom layer during the re-flow process.
37 ? 2006 semtech corp. www.semtech.com power management sc2441a outline drawing - tssop-28 semtech corporation power management products division 200 flynn road, camarillo, ca 93012-8790 phone: (805)498-2111 fax (805)498-3804 contact information land pattern - tssop-28 n a a2 a1 bxn e1 .378 9.60 .386 9.70 9.80 plane bbb c a-b d ccc c dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view a b c d e h e/2 (.039) .008 - .004 .024 - - - - 0 .018 .003 e inches b n bbb aaa ccc 01 e1 e l l1 e d c dim a1 a2 a min max millimeters dimensions min max nom nom .210 f 5.60 5.35 .220 .216 5.50 h .112 3.10 .118 .122 3.00 2.85 bottom view exposed pad f h .031 .000 - 8 0 0.20 0.10 - 8 0.45 0.09 0.80 0.00 .030 .008 .047 .041 .006 - 0.60 (1.0) - 0.75 0.20 - - - 1.20 1.05 0.15 d reference jedec std mo-153, variation aet. 4. l (l1) c 01 gage plane see detail detail a a 0.25 .026 bsc .252 bsc 28 .004 .169 .173 .007 - 28 0.10 0.65 bsc 6.40 bsc 4.40 - .177 4.30 .012 0.19 4.50 0.30 .382 2x n/2 tips seating aaa c e/2 indicator pin 1 2x 2 13 (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. f h inches dimensions z p y x dim c g millimeters f 5.70 .224 h 3.20 .126

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